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pci-express clock generator ic, pll core, dividers, two outputs ad9573 features fully integrated vco/pll core 0.54 ps rms jitter from 12 khz to 20 mhz input crystal frequency of 25 mhz preset divide ratios for 100 mhz, 33.33 mhz lvds/lvcmos output format integrated loop filter space saving 4.4 mm 5.0 mm tssop 0.235 w power dissipation 3.3 v operation applications line cards, switches, and routers cpu/pcie applications low jitter, low phase noise clock generation general description the ad9573 provides a highly integrated, dual output clock generator function including an on-chip pll core that is optimized for pci-e applications. the integer-n pll design is based on the analog devices, inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize line card performance. other applications with demanding phase noise and jitter requirements also benefit from this part. the pll section consists of a low noise phase frequency detector (pfd), a precision charge pump, a low phase noise voltage controlled oscillator (vco), and a preprogrammed feedback divider and output divider. by connecting an external 25 mhz crystal, output frequencies of 100 mhz and 33.33 mhz can be locked to the input reference. the output divider and feedback divider ratios are prepro- grammed for the required output rates. no external loop filter components are required, thus conserving valuable design time and board space. the ad9573 is available in a 16-lead 4.4 mm 5.0 mm tssop and can be operated from a single 3.3 v supply. the temperature range is ?40c to +85c. functional block diagram v dd 5 oe gnd 5 ad9573 xtal osc vco pfd/cp 3rd order lpf dividers ldo 100mhz lvds lvcmos 33.33mhz 07500-001 figure 1. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved.
ad9573 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? pll characteristics ...................................................................... 3 ? clock output jitter ....................................................................... 3 ? clock outputs ............................................................................... 3 ? timing characteristics ................................................................ 4 ? control pins .................................................................................. 4 ? power .............................................................................................. 4 ? crystal oscillator .......................................................................... 4 ? timing diagrams .......................................................................... 4 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution...................................................................................5 ? pin configuration and function descriptions ..............................6 ? typical performance characteristics ..............................................7 ? terminology .......................................................................................8 ? theory of operation .........................................................................9 ? outputs ...........................................................................................9 ? phase frequency detector (pfd) and charge pump ..........9 ? power supply ..................................................................................9 ? lvds clock distribution .......................................................... 10 ? cmos clock distribution ........................................................ 10 ? power and grounding considerations and power supply rejection ...................................................................................... 10 ? outline dimensions ....................................................................... 11 ? ordering guide .......................................................................... 11 ? revision history 7/09revision 0: initial version
ad9573 rev. 0 | page 3 of 12 specifications typical (typ) is given for v dd = 3.3 v 10%, t a = 25c, unless otherwise noted. minimum (min) and maximum (max) values are given over full v dd and t a (?40c to +85c) variation. pll characteristics table 1. parameter min typ max unit test conditions/comments noise characteristics pll noise (100 mhz output) @ 1 khz ?121 dbc/hz @ 10 khz ?128 dbc/hz @ 100 khz ?131 dbc/hz @ 1 mhz ?144 dbc/hz @ 10 mhz ?150 dbc/hz @ 30 mhz ?151 dbc/hz pll noise (33.33 mhz output) @ 1 khz ?131 dbc/hz @ 10 khz ?137 dbc/hz @ 100 khz ?140 dbc/hz @ 1 mhz ?150 dbc/hz @ 5 mhz ?151 dbc/hz spurious content ?70 dbc pll figure of merit ?217.5 dbc/hz clock output jitter table 2. parameter min typ max unit test conditions/comments lvds output absolute time jitter rms jitter (100 mhz output) 540 fsec 12 khz to 20 mhz clock outputs table 3. parameter min typ max unit test conditions/comments lvds clock output termination = 100 differential output frequency 100 mhz differential output voltage (v od ) 500 640 700 mv delta v od 25 mv output offset voltage (v os ) 1.125 1.25 1.375 v delta v os 25 mv short-circuit current (i sa , i sb ) 14 24 ma output shorted to gnd duty cycle 45 55 % lvcmos clock output output frequency 33.33 mhz output high voltage (v oh ) v s ? 0.1 v sourcing 1.0 ma current output low voltage (v ol ) 0.1 v sinking 1.0 ma current duty cycle 45 55 %
ad9573 rev. 0 | page 4 of 12 timing characteristics table 4. parameter min typ max unit test conditions/comments lvds termination = 100 differential; c load = 0 pf output rise time, t rl 140 200 260 ps 20% to 80%, measured differentially output fall time, t fl 140 200 260 ps 80% to 20%, measured differentially lvcmos termination = open output rise time, t rc 0.25 0.60 2.5 ns 20% to 80%; c load = 5 pf output fall time, t fc 0.25 0.80 2.5 ns 80% to 20%; c load = 5 pf control pins table 5. parameter min typ max unit test conditions/comments input characteristics oe pin oe has a 50 k pull-down resistor. logic 1 voltage 2.5 v logic 0 voltage 0.8 v logic 1 current 120 a logic 0 current 1.0 a power table 6. parameter min typ max unit test conditions/comments power supply 3.0 3.3 3.6 v power dissipation 235 285 mw crystal oscillator table 7. parameter min typ max unit test conditions/comments crystal specification parallel resonant/fundamental mode frequency 25 mhz esr 40 load capacitance 18 pf phase noise ?138 dbc/hz @ 1 khz offset stability ?30 +30 ppm timing diagrams differential signal v od 80% 20% 50% single-ended cmos 5pf load 80% 20% t rc t rl t fl 07500-003 figure 2. lvds timing, differential t fc 0 7500-004 figure 3. lvcmos timing
ad9573 rev. 0 | page 5 of 12 absolute maximum ratings table 8. parameter rating vdd, vdda, vddx, and vdd33 to gnd ?0.3 v to +3.6 v xo1, xo2 to gnd ?0.3 v to v s + 0.3 v 100m, 100m , 33m to gnd ?0.3 v to v s + 0.3 v junction temperature 1 150c storage temperature range ?65c to +150c lead temperature (10 sec) 300c 1 see table 9 for ja. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. thermal impedance measurements were taken on a 4-layer board in still air in accordance with eia/jesd51-7. table 9. thermal resistance package type ja unit 16-lead tssop 90.3 c/w esd caution a 1 2 3 4 5 6 7 8 vdda vddx xo1 gnda gndx xo2 gnda vdda 16 15 14 13 gnd 100m 100m 33m gnd3 vdd3 vdd oe 12 11 10 9 3 3 d9573 50 ? r t = 100? 50 ? 1nf 0.1f 0.1f 0. vs 1f vs vs 0.1f 0.1f cx cx crystal: kyocera cx-49g cx = 33pf vs vs 07500-002 figure 4. typical application
ad9573 rev. 0 | page 6 of 12 pin configuration and fu nction descriptions 1 2 3 4 5 6 vdda vddx xo1 7 8 g nda vdda gndx xo2 gnda 16 15 14 13 12 11 gnd 100m 100m vdd33 vdd oe top view (not to scale) ad9573 10 9 33m gnd33 07500-005 figure 5. pin configuration table 10. pin function descriptions pin no. mnemonic description 1, 7 gnda analog ground. 2, 8 vdda analog power supply (3.3 v). 3 vddx crystal oscillator power supply. 4, 5 xo1, xo2 external 25 mhz crystal. 6 gndx crystal oscillator ground. 9 gnd33 ground for lvcmos output. 10 33m lvcmos output at 33.33 mhz. 11 vdd33 power supply for lvcmos output. 12 vdd power supply for lvds output. 13 100m complementary lvds output at 100 mhz. 14 100m lvds output at 100 mhz. 15 gnd ground for lvds output. 16 oe output enable (active low). places both outputs in a hi gh impedance state when high. this pin has a 50 k internal pull-down resistor.
ad9573 rev. 0 | page 7 of 12 07500-006 typical performance characteristics ? 115 ?145 ?135 ?125 ?120 ?150 ?140 ?130 phase noise (dbc/hz) ?155 1k 10k 100k 1m 10m 100m frequency offset (hz) figure 6. 100 mhz phase noise 0750 ? 120 ?130 ?140 ?150 ?160 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency offset (hz) 0-007 figure 7. 33.33 mhz phase noise
ad9573 rev. 0 | page 8 of 12 terminology phase jitter an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 degrees to 360 degrees for each cycle. actual signals, however, display a certain amount of variation from ideal phase progression over time. this phenomenon is called phase jitter. although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as gaussian (normal) in distribution. this phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. this power spectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). the value is a ratio (expressed in db) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. phase noise when the total power contained within some interval of offset frequencies (for example, 12 khz to 20 mhz) is integrated, it is called the integrated phase noise over that frequency offset interval, and it can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimental effect on error rate performance by increasing eye closure at the transmitter output and reducing the jitter tolerance/sensitivity of the receiver. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect is exhibited as time jitter. when observing a sine wave, the time of successive zero crossings is seen to vary. in a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. in both cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the gaussian distribution. additive phase noise additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. the phase noise of any external oscillators or clock sources has been subtracted. this makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. additive time jitter additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. the time jitter of any external oscillators or clock sources has been subtracted. this makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
ad9573 rev. 0 | page 9 of 12 theory of operation xtal osc phase frequency detector charge pump divide by 4 divide by 3 cmos 33.33mhz 33m vdda gnda vdda gnda v dd, vdd33 gnd, gnd33 oe divide by 25 2.5ghz vco ldo 100m 100m lvds 100mhz v ldo ad9573 07500-011 figure 8. detailed block diagram figure 8 shows a block diagram of the ad9573. the chip features a pll core, which is configured to generate the specific clock frequencies required for pci-express, without any user programming. this pll is based on proven analog devices synthesizer technology, noted for its exceptional phase noise performance. the ad9573 is highly integrated and includes the loop filter, a regulator for supply noise immunity, all the necessary dividers, output buffers, and a crystal oscillator. a user need only supply a 25 mhz external crystal to implement an entire pcie clocking solution, which does not require any processor intervention. outputs table 11 provides a summary of the outputs available. table 11. output formats frequency format copies 100 mhz lvds 1 33.33 mhz lvcmos 1 the simplified equivalent circuit of the lvds output is shown in figure 9 . the 100 mhz output is described as lvds because it uses an lvds driver topology. however, the levels are hcsl compatible, and therefore do not meet the lvds standard. the output current has been increased to provide a larger output swing than standard lvds. 6.5ma 6.5ma out outb 0750 0-012 figure 9. lvds output simplified equivalent circuit both outputs can be placed in a high impedance state by connecting the oe pin according to . this pin has a 50 k pull-down resistor. tabl e 12 table 12. output enable pin function oe state output state 0 enabled 1 high impedance phase frequency detector (pfd) and charge pump the pfd takes inputs from the reference clock and feedback divider to produce an output proportional to the phase and frequency difference between them. figure 10 shows a simplified schematic. 0 7500-013 d1 q1 clr1 refclk high up d2 q2 clr2 high down cp charge pump 3.3 v gnd feedback divider figure 10. pfd simplified sche matic and timing (in lock) power supply the ad9573 requires a 3.3 v 10% power supply for vdd. the tables in the specifications section give the performance expected from the ad9573 with the power supply voltage within this range. the absolute maximum range of (?0.3 v) ? (+3.6 v), with respect to gnd, must never be exceeded on the vdd or vdda pins. good engineering practice should be followed in the layout of power supply traces and the ground plane of the pcb. the power supply should be bypassed on the pcb with adequate capacitance (>10 f). the ad9573 should be decoupled with adequate capacitors (0.1 f) at all power pins as close as possible to these power pins. the layout of the ad9573
ad9573 rev. 0 | page 10 of 12 evaluation board shows a good example (see the ordering guide for information about the evaluation board). lvds clock distribution low voltage differential signaling ( lvds) is the differential output for the ad9573. lvds uses a current mode output stage with a factory programmed current level. the normal value (default) for this current is 6.5 ma, which yields a 650 mv output swing across a 100 resistor. the typical termination circuit for the lvds outputs is shown in figure 11 . 50? 50? lvds lvds 100? 0 7500-014 figure 11. lvds output termination an alternative method of terminating the output to preserve output swing but also minimize reflections is shown in figure 12 . 50? 50? lvds lvds 200? 200 ? 0 7500-015 figure 12. alternative lvds output termination cmos clock distribution the ad9573 provides a 33.33 mhz clock output, which is a dedicated cmos level. whenever single-ended cmos clocking is used, some of the following general guidelines should be followed. point-to-point nets should be designed such that a driver has one receiver only on the net, if possible. this allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. the value of the resistor is dependent on the board design and timing requirements (typically 10 to 100 is used). cmos outputs are limited in terms of the capacitive load or trace length that they can drive. typically, trace lengths less than 6 inches are recommended to preserve signal rise/fall times and preserve signal integrity. 10 ? microstrip gnd 5pf 60.4 ? 1.0 inch cmos 0 7500-016 figure 13. series termination of cmos output termination at the far end of the pcb trace is a second option. the cmos output of the ad9573 does not supply enough current to provide a full voltage swing with a low impedance resistive, far end termination, as shown in figure 14 . the far end termination network should match the pcb trace impedance and provide the desired switching point. the reduced signal swing may still meet receiver input require- ments in some applications. this can be useful when driving long trace lengths on less critical nets. v pullup = 3.3 v 50? 10? cmos 3pf 100 ? 100 ? 0 7500-017 figure 14. cmos output wi th far-end termination power and grounding considerations and power supply rejection many applications seek high speed and performance under less than ideal operating conditions. in these application circuits, the implementation and construction of the pcb is as important as the circuit design. proper rf techniques must be used for device selection, placement, and routing, as well as for power supply decoupling and grounding to ensure optimum performance.
ad9573 rev. 0 | page 11 of 12 outline dimensions 16 9 8 1 4.50 4.40 4.30 pin 1 seating plane 8 0 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 15. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model temperature range packag e description package option ad9573aruz 1 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 AD9573-EVALZ 1 evaluation board 1 z = rohs compliant part.
ad9573 rev. 0 | page 12 of 12 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07500-0-7/09(0)

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